The present invention relates to a nonvolatile semiconductor memory device having a redundancy function.
In order to improve the yield, the nonvolatile semiconductor memory device has a redundancy function for replacing a defective bit line, a defective word line and a defective memory cell with normal ones. The nonvolatile semiconductor memory device having such a redundancy function is required to store the addresses of the defective bit line, defective word line and defective memory cell.
Conventionally, the most general method for storing the addresses of the defective bit line, defective word line and defective memory cell (the addresses being referred to as a defective address hereinafter), there is the one that employs a fuse as disclosed in the prior art references of Japanese Patent Laid-Open Publication Nos. HEI 2-307245 and HEI 6-150689. According to this method, when storing a 3-bit address, as shown in FIG. 8, if the defective address is, for example, "101", then a fusel is cut. The specifying of the defective address and the cutting of the fuse are executed in a device testing stage.
After the completion of the above-mentioned test, the device practically operates as follows. If a power voltage Vcc rises and the level of a signal rdcamen goes high to turn on transistors 1 through 3, then input voltages of inverters 4 and 6 are pulled up to a voltage Vss via a fuse0 and a fuse2. Consequently, the outputs of the inverters 4 and 6, i.e., the levels of address signals rdadd0 and rdadd2 are latched to the high level. On the other hand, the input voltage of an inverter 5 maintains the high level since the fusel is cut. Consequently, the output of the inverter 5, i.e., the level of the address signal rdadd1 is latched to the low level. The defective address "101" is thus set.
In this case, what becomes the most serious problem is the layout area of the portions of the fuse0 through fuse2. In accordance with the progress in density of integration and the increase in number of defective addresses for storage, the fuses are increased in number to increase the layout area of the fuses, and this requires a reduction in layout area of the fuses.
In view of the above, as a method for solving the aforementioned problems, there is the method of employing electrically writable nonvolatile semiconductor memory cells in place of the fuses, as disclosed in the prior art reference of Japanese Patent Laid-Open Publication No. HEI 5-276018. The circuit diagram of one example of the above is shown in FIG. 9. In this defective address setting circuit, electrically writable nonvolatile semiconductor memory cells having a floating gate (referred to simply as memory cells hereinafter) M0 through M2 are arranged in place of the fuse0 through fuse2 in the circuit shown in FIG. 8. This defective address setting circuit is further provided with a column decoder for selectively turning on the illustrated transfer gates by bit selection signals bitse10 through bitse12, a data latching function for writing defective address data and a level shifter.
The following will describe the setting of the defective address "101" with this defective address setting circuit. The defective address setting circuit shown in FIG. 9 is the circuit applied to a flash memory for executing writing with channel hot electrons represented by ETOX (brand name of Intel Corporation). In the flash memory of this type, the threshold value of the memory cell M is about 0.5 V to 1.5 V in the initial state. Writing into this memory cell M is executed with hot electrons as follows.
First, if the level of a data line 11 in FIG. 9 goes high, then low-level write data is latched into a write data latch circuit 12. The word line WL of the memory cell M0 is raised up to Vpp (10 V, for example) and the level of the bit selection signal bitse10 becomes Vpp. In this stage, a transistor 14 has a gate voltage of 0 V since the output level of a level shifter (HV) 13 is latched to the low level, so that the transistor 14 is turned off. Consequently, the bit line BL0 is brought into a floating state and the threshold value of the memory cell M0 is maintained in a low state (1.5 V or lower). Next, if the level of the data line 11 goes low, then the high-level write data is latched into the write data latch circuit 12. The word line WL of the memory cell M1 is raised to Vpp, and the level of the bit selection signal bitse11 becomes Vpp. In this stage, the gate voltage of the transistor 14 becomes Vpp since the output level of the level shifter circuit 13 is latched to the high level, so that the transistor 14 is turned on. Consequently, the voltage of the bit line BL1 becomes hhprg (6 V, for example), and the threshold value of the memory cell M1 increases due to the channel hot electrons. Subsequently, the data line 11 goes low and the word line WL is raised up to Vpp. If the level of the bit selection signal bitse12 becomes Vpp, then the threshold value of the memory cell M2 is maintained in the low state, similarly to the case of the memory cell M0. The specifying of the defective address and the writing into the corresponding memory cell M is executed in the device testing stage.
After the completion of the aforementioned test, the device practically operates as follows. If the power voltage Vcc (3 V, for example) rises, the word line WL rises to Vcc and the level of the signal rdcamen goes high to turn on transistors 15 through 17, then the memory cells M0 and M2 of the low threshold value are turned on to pull the input voltages of inverters 18 and 20 up to Vss. Consequently, the outputs of the inverters 18 and 20, i.e., the address signals rdadd0 and rdadd2 are latched to the high level. On the other hand, the input voltage of an inverter 19 is maintained at the high level since the memory cell M1 of the high threshold value is turned off. Consequently, the output of the inverter 19, i.e., the address signal rdadd1 is latched to the low level. The defective address "101" is thus set.
Thus, the defective address is set and stored in the flash memory of the channel hot electron type. There is another problem of "disturbance" that must be considered to be solved in the case of the flash memory. In this case, particularly the gate disturbance in the writing stage emerges as a problem. Writing conditions in the case where the channel hot electrons are used are as shown in FIG. 10 and the writing speed per cell is about 1 .mu.sec. Therefore, in the case of the system in which sequential writing is executed every cell according to the aforementioned procedure, assuming that, for example, 256 cells undergo the sequential writing, then there is the resulting disturbance time interval of 255 .mu.sec under the most severe conditions. This interval is very short as the disturbance time and assures a sufficient tolerance, and accordingly, there is no problem.
The memory cells employed in the main storage circuit and the redundancy storage circuit are formed in the same style. Therefore, if a flash memory of FN (Fowler-Nordheim)--FN type flash memory is employed in the main storage circuit, differently from the flash memory of the channel hot electron type, then a nonvolatile semiconductor memory cell of the FN--FN type is to be used for the redundancy storage circuit and the nonvolatile semiconductor memory cell array for defective address writing use. Therefore, a defective address setting circuit in the case where the defective address of the flash memory of the FN--FN type is set and stored by the electrically writable nonvolatile semiconductor memory cells is as shown in FIG. 11.
In this case, the reason why the defective address setting circuit as shown in FIG. 9 cannot be used in the case of the flash memory of the FN--FN type is as follows. That is, the flash memory of the FN--FN type has a writing speed of about 1 msec per cell, which is slower than in the flash memory of the channel hot electron type. The disturbance conditions in this case are as shown in FIG. 12. If 256 cells are subjected to the sequential writing, then the disturbance time interval accumulates to 255 msec, which is so long that a change in threshold value is disadvantageously caused when the defective address setting circuit as shown in FIG. 9 is adopted. Therefore, the circuit construction as shown in FIG. 11 is necessary. According to this circuit construction, it is enabled to suppress the occurrence of disturbance since the writing is executed at a time on the corresponding memory cells of the nonvolatile semiconductor memory cell array after executing latching in the write latch circuits corresponding to the pieces of defective address data.
The operation of the defective address setting circuit shown in FIG. 11 will be described below. In this case, the memory cells M0 through M2 are initially brought in a high threshold value state for the erasing. The erasing is executed by applying a voltage Vns (-8 V, for example) to the substrate on which a common source and a memory cell M are formed, bringing each bit line BL in an open state and applying a voltage Vpp (10 V, for example) to the word line WL. The erasing is thus executed by increasing the threshold value to 4 V or higher with electrons injected from the channel region into the floating gate.
Subsequently, the defective address data are written into a nonvolatile semiconductor memory cell array 27 as follows. Initially, the defective address data are transferred to the latches of a write latch circuit 26. First, the level of a data line 21 goes high and the level of the signal bitse10 goes high to turn on the transistor 23 of a column decoder 22, by which the high level is latched in the latch0 of the write latch circuit 26. Subsequently, the level of the data line 21 goes low and the level of the signal bitse11 goes high to turn on a transistor 24, by which the low level is latched in the latch1 of the write latch circuit 26. Subsequently, if the level of the data line 21 goes high similarly, then the level of the bitse12 goes high to turn on a transistor 25, and the high level is latched in the write latch circuit 26.
Subsequently, if the voltage of the word line WL of the nonvolatile semiconductor memory cell array 27 becomes Vnn (-8 V, for example), the voltage of the signal hhprg of the write latch circuit 26 becomes Vpg (5 V, for example) and a signal rdpgen becomes Vpps (7 V, for example), then a voltage of 5 V is applied to the bit lines BL0 and BL2 since the high level is latched in the latch0 and the latch2. By the above operation, a FN tunneling phenomenon occurs on the drain side of the memory cells M0 and M2, so that electrons are drawn to the drain side to reduce the threshold voltage to 1.5 V or lower. In contrast to this, a voltage of 0 V is applied to the bit line BL1 since the low level is latched in the latch1. By the above operation, the threshold voltage of the memory cell M1 is maintained at 4 V or higher.
The defective address setting circuit in which the defective address is thus set operates as follows when practically used as a device. If the power voltage Vcc (3 V, for example) rises, then the voltages of the word line WL of the nonvolatile semiconductor memory cell array 27 and the signal rdcamen rises to the power voltage Vcc. Then, the memory cells M0 and M2 of which the threshold value is reduced to 1.5 V or lower are turned on, while the memory cell M1 of which the threshold value is maintained at 4 V or higher is turned off. Therefore, similar to the case of the fuses of the defective address setting circuit shown in FIG. 8, the input voltages of inverters 29 and 31 of a defective address latch circuit 28 is pulled up to the common source (voltage Vss) via the memory cells M0 and M2. Consequently, the outputs of the inverters 29 and 31, i.e., the levels of the address signals rdadd0 and rdadd2 are latched to the high level. On the other hand, the input voltage of an inverter 30 maintains the high level since the memory cell M1 is in the off state. Consequently, the output of the inverter 30, i.e., the level of the address signal rdadd1 is latched to the low level. The defective address "101" is thus set.
If the defective address is stored in the electrically writable nonvolatile semiconductor memory as described above, then it is enabled to reduce the layout area as compared with the case where the fuses are used.
However, when storing the defective address into the nonvolatile semiconductor memory cell array in the conventional flash memory of the FN--FN type, the defective address setting circuit is constructed of the defective address latch circuit 28, the nonvolatile semiconductor memory cell array 27, the write latch circuit 26 and the column decoder 22. As described above, when using the flash memory of the EN--FN type, the write latch circuit 26 having the latch0 through latch2 must be provided for each memory cell M in relation to the gate disturbance in the writing stage. Accordingly, there is the problem that the layout area is increased by the write latch circuit 26 than in the case of the flash memory of the channel hot electron type.